1. Field of the Invention
The present invention relates generally to methods for forming titanium nitride layers within integrated circuits. More particularly, the present invention relates to methods for forming low resistance chemical vapor deposited (CVD) titanium nitride layers within integrated circuits.
2. Description of the Related Art
Generally known in the art of integrated circuit fabrication is the use of titanium nitride layers. Titanium nitride layers within integrated circuit fabrication are most commonly employed as either adhesion promoter layers or barrier layers. When employed as adhesion promoter layers, titanium nitride layers within integrated circuits are typically formed as liner layers beneath blanket tungsten layers from which in turn are formed conductive contact and interconnection studs through patterned dielectric layers within those integrated circuits. Alternatively, when employed as barrier layers, titanium nitride layers are typically formed interposed between an aluminum containing conductor metallization layer and a doped silicon layer or a doped silicon semiconductor substrate. When formed in this location, a titanium nitride layer provides a barrier to inhomogeneous interdiffusion and spiking from the aluminum containing conductor metallization layer into the doped silicon layer or the doped silicon semiconductor substrate. Titanium nitride layers which are employed as barrier layers are particularly well evolved within integrated circuit fabrication. See, for example, Ngan et al., who disclose in U.S. Pat. No. 5,378,660 and U.S. Pat. No. 5,504,043 the use of a sequential annealing method to form a titanium silicide/titanium nitride/titanium oxynitride composite barrier layer for use beneath aluminum layers formed at high temperatures within integrated circuits.
While the barrier layer characteristics of titanium nitride layers and the adhesive layer characteristics of titanium nitride layers have made titanium nitride layers quite common within integrated circuit fabrication, methods through which such titanium nitride layers may be formed within integrated circuits are not entirely without problems. In particular, as integrated circuits device dimensions have decreased, and aspect ratios of apertures within which titanium nitride layers are desired to be formed within those integrated circuits have increased it has become increasingly difficult to form, through conventional physical vapor deposition (PVD) sputtering methods, titanium nitride layers with adequate step coverage. The difficulty derives from the inherent line-of-sight deposition characteristics of conventional physical vapor deposition (PVD) sputtering methods employed in forming integrated circuit layers of titanium nitride, as well as other materials. The line-of-sight deposition characteristics typically provide only limited sidewall and bottom coverage of titanium nitride within a narrow high aspect ratio aperture (ie: an aperture of width less than about 0.5 microns and aspect ratio greater than about 3) within which is desired to form a titanium nitride layer, in comparison with titanium nitride coverage upon the surface of the integrated circuit layer (typically a dielectric layer) within which is formed the aperture.
In response to the step coverage limitations inherent in forming titanium nitride layers through physical vapor deposition (PVD) sputtering methods, there has alternatively been proposed and disclosed the use of chemical vapor deposition (CVD) methods for forming titanium nitride layers within integrated circuits. Titanium nitride layers formed through chemical vapor deposition (CVD) methods have inherently superior step coverage within narrow high aspect ratio apertures within integrated circuits since chemical vapor deposition (CVD) methods, in general, proceed through a surface diffusion deposition phenomenon rather than a line-of-sight deposition phenomenon.
While chemical vapor deposition (CVD) methods may be employed within integrated circuits to provide titanium nitride layers with superior step coverage for narrow high aspect ratio apertures formed within those integrated circuits, chemical vapor deposition (CVD) methods are also not entirely without problems in forming within integrated circuits titanium nitride layers with optimally desirable properties. In that regard, it is known in the art that titanium nitride layers formed through chemical vapor deposition (CVD) methods, while possessing superior step coverage characteristics, are also difficult to form at comparatively low temperatures (ie: less than a temperature of about 550 degrees centigrade at which aluminum containing conductor metallization layers deteriorate) simultaneously with low resistivity and low impurity concentrations. A particularly undesirable impurity formed within titanium nitride layers deposited through such low temperature chemical vapor deposition (CVD) methods is halogen impurities, most typically chlorine impurities. The halogen impurities found within a titanium nitride layer formed through a low temperature chemical vapor deposition (CVD) method may result from halogens intrinsically present within a titanium source material employed in forming the titanium nitride layer (see, for example, Foster et al., in U.S. Pat. No. 5,378,501, who disclose titanium nitride layers formed through a low temperature chemical vapor deposition (CVD) method employing a titanium tetrachloride source material) or halogens employed extrinsically in forming the titanium nitride layer (see, for example, Sandhu, in U.S. Pat. No. 5,399,379, who discloses titanium nitride layers formed through a low temperature chemical vapor deposition (CVD) method employing a tetrakis-dialkylamido titanium (ie: Ti(NR2)4) primary source material in conjunction with an extrinsic halogen activator secondary source material). Unfortunately, the presence of halogens within titanium nitride layers formed within integrated circuits through low temperature chemical vapor deposition (CVD) methods is undesirable since the presence of halogens provides titanium nitride layers which are prone to corrosion and electrical leakage. Other undesirable impurities typically found within titanium nitride layers formed through low temperature chemical vapor deposition (CVD) methods employing a tetrakis-dialkylamido titanium primary source material include but are not limited to carbon impurities and oxygen impurities. These impurities typically provide titanium nitride layers of undesirably high sheet resistance.
It is therefore desirable in the art to provide methods and materials through which there may be formed within advanced integrated circuits titanium nitride layers through low temperature chemical vapor deposition (CVD) methods to provide titanium nitride layers which in addition to possessing superior step coverage also simultaneously possess low resistivity and low impurity levels. It is towards those goals that the present invention is specifically directed.